The present invention relates generally to numeric processing, such as used in communication signal processing contexts, and particularly relates to multiply-and-accumulate operations.
A multiply-and-accumulate (MAC) operation multiplies two numbers and adds the result to a saved value or, more generally, to an accumulation register. Useful results, such as signal filtering in the digital domain, are obtained by repeating this operation for a series of number pairs.
A conventional approach to performing a desired series of MAC operations requires performing a full precision multiply operation and a full precision addition operation for each number pair in the series. The implementation of conventional MAC operations in software may result in undesirable performance penalties. Performance can be significantly improved by providing dedicated MAC hardware in the form of appropriately interconnected adders/multipliers and control logic. However, performing MAC operations at high rates, such as those associated with digital signal processing in the wireless communication domain, requires very high-speed adders and multipliers. Such hardware may be impractical, at least for some integrated circuit processes, or may be prohibitively expensive or power hungry.